1. Field of the Invention
The present invention relates to a phase comparator for comparing difference in phase between a transient edge of an input data signal and transient edges of clock signals, a clock data recovery (hereinafter abbreviated as “CDR”) circuit for adjusting the differences in phase, and a transceiver circuit using the phase comparator.
2. Background Art
FIG. 1 shows a block diagram of a conventional CDR circuit. In FIG. 1, reference numeral 130 indicates the conventional CDR circuit, and reference numeral 131 indicates an input terminal of an input data signal Din. Reference numeral 133 indicates a phase comparator for inputting the input data signal Din inputted from the input terminal 131 and a clock signal ckv outputted from a voltage controlled oscillator (VCO) to be described later to thereby compare the phases thereof, or a phase detector (PD) or a phase frequency detector (PFD) for detecting the difference in phase therebetween (the circuit designated at numeral 133 will hereinafter be called “phase detector PD”). Subsequently, reference numeral 135 indicates a charging pump (CP) which inputs a reference signal (Ref) and an error signal (Error) outputted from the phase detector PD (133) and thereby outputs a charge current and a discharge current, and reference numeral 137 indicates a loop filter (shown around by a broken line) which is made up of a resistor R3 (139), a capacitor C2 (141), and a resistor R4 (143) connected in series and takes out a dc component from the charge current or the discharge current outputted from the charging pump CP (135). The loop filter 137 averages the charge current or the discharge current on a time basis and represents the averaged one as the difference in potential between vcont+ and vcont−. Reference numeral 145 indicates a double/single-phase voltage converter (DSC) for converting the difference in potential between vcont+ and vcont− taken out from the loop filter 137 to a desired voltage vcont, and reference numeral 147 indicates a voltage controlled oscillator VCO for outputting the clock signal ckv according to the desired voltage vcont outputted from the double/single-phase voltage controller DSC (145) and receiving it as the input of the phase detector PD (133).
While the output of the charging pump 135 is a differential signal and the loop filter 137 also shows a differential configuration, a configuration using a single-phase output charging pump and a single-phase loop filter is also normally adopted. In the case of the single-phase configuration, a circuit such as a voltage follower circuit or the like is used without using the double/single-phase voltage converter 145.
The operation of the CDR circuit 130 will next be described. As shown in FIG. 1, the conventional CDR circuit 130 is a circuit which causes the input data signal Din (whose frequency f/2 Hz or bit rate f bits/sec) inputted from the input terminal 131 and the clock signal ckv outputted from the voltage controlled oscillator VCO (147) to coincide in frequency and phase with each other. Namely, the CDR circuit 130 performs the operation of feeding back the difference in phase between the input data signal Din and the clock signal ckv to its corresponding oscillation frequency of the voltage controlled oscillator VCO (147) and allowing the phase of the clock signal ckv to coincide with that of the input data signal Din. The CDR circuit 130 is brought to a lock state in which both signals coincide with each other when the rising edge of the clock signal ckv is placed in the center (time equivalent to one-half a cycle or period T) of a time width (cycle T=1/f) of the input data signal Din. In the lock state, latches 150, 151, 152, 153 (shown in FIG. 2) lying inside the phase detector PD (133) latch and shape the input data signal Din according to the clock signal ckv and output two output signals. One of the two output signals is corresponding to even (odd) number of the input data signal Din and the output signal q3 of latch 152 from an output terminal 148 as a Dout 1 signal corresponding to the output of the CDR circuit 130. Another one of the two output signals is corresponding to odd (even) number of the input data signal Din and the output signal q4 of latch 153 from an output terminal 146 as a Dout 2 signal corresponding to the output of the CDR circuit 130. The clock signal ckv is outputted from an output terminal 149 as a Ckout signal.
The conventional phase detector PD (133) for detecting the difference in phase between the input data signal Din and the clock signal ckv is a circuit for outputting an error signal (Error) and a reference signal (Ref) and setting the difference between pulse widths of the two signals as the phase difference referred to above.
FIG. 2 shows a block diagram of the conventional phase detector PD (133). In FIG. 2, reference numeral 154 indicates an input terminal of an input data signal Din, reference numeral 155 indicates an input terminal of a clock signal ckv, reference numerals 150, 151, 152 and 153 indicate latches L1, L2, L3 and L4 respectively having D terminals of their data inputs, C terminals of their clock inputs and Q outputs, reference numerals 156 and 157 indicate exclusive-OR circuits, reference numeral 160 indicates an output terminal of an error signal (Error), and reference numeral 161 indicates an output terminal of a reference signal (Ref), respectively.
The latch L1 (150) latches the input data signal Din inputted to the D terminal on the rising edge of the clock signal ckv inputted to the C terminal and outputs the Din to the Q output (q1). While the clock signal ckv inputted to the C terminal is High (logical 1), the latch L1 (150) holds the Q output (q1) as it is. On the other hand, the latch L1 (150) outputs the input data signal Din to the Q output (q1) as it is while the clock signal ckv inputted to the C terminal is Low (logical 0). Accordingly, when the input data signal Din changes while the clock signal ckv inputted to the C terminal is Low (logical 0), the Q output (q1) also changes according to its change.
The latch L2 (151) latches the input data signal Din inputted to the D terminal on the falling edge of the clock signal ckv inputted to the C terminal and outputs the Din to the Q output (q2). While the clock signal ckv inputted to the C terminal is Low (logical 0), the latch L2 (151) holds the Q output (q2) as it is. On the other hand, the latch L2 (151) outputs the input data signal Din to the Q output (q2) as it is while the clock signal ckv inputted to the C terminal is High (logical 1). Thus, when the input data signal Din changes while the clock signal ckv inputted to the C terminal is High (logical 1), the Q output (q2) also changes according to its change.
The Q output (q1) of the latch L1 (150) and the Q output (q2) of the latch L2 (151) are inputted to the exclusive-OR circuit 156. An output q1 xor q2 (where “xor” means XORing (exclusive OR) of q1 and q2. This is hereinafter similar.) thereof is outputted from the output terminal 160 as the error signal (Error).
The latch L3 (152) latches the Q output (q1) inputted to the D terminal on the falling edge of the clock signal ckv inputted to the C terminal and outputs it to the Q output (q3). While the clock signal ckv inputted to the C terminal is Low (logical 0), the latch L3 (152) holds the Q output (q3) as it is. On the other hand, the latch L3 (152) outputs the input Q output (q1) to the Q output (q3) as it is while the clock signal ckv inputted to the C terminal is High (logical 1).
The latch L4 (153) latches the Q output (q2) inputted to the D terminal on the rising edge of the clock signal ckv inputted to the C terminal and outputs it to the Q output (q4). While the clock signal ckv inputted to the C terminal is High (logical 1), the latch L4 (153) holds the Q output (q4) as it is. On the other hand, the latch L4 (153) outputs the input Q output (q2) to the Q output (q4) as it is while the clock signal ckv inputted to the C terminal is Low (logical 0).
The Q output (q3) of the latch L3 (152) and the Q output (q4) of the latch L4 (153) are inputted to the exclusive-OR circuit 157. An output q3 xor q4 thereof is outputted from the output terminal 161 as the reference signal (Ref).
FIGS. 3(A) through 3(H) show a time chart of the conventional phase detector PD (133) shown in FIG. 2. Since spots or parts marked with the same reference numerals as those shown in FIG. 2 indicate the same parts in FIGS. 3(A) through 3(H), their description will be omitted. A signal shown in FIG. 3(A) shows that the name thereof indicates the input data signal Din and the speed thereof (the fastest speed expressed in Hz conversion and similar subsequently) is expressed in f/2 (data period or cycle is given by T (=1/f)). The signal is expressed in the form of data 0, data 1, etc. for each cycle T. A signal shown in FIG. 3(B) indicates that the name thereof is represented as the clock signal ckv, the speed thereof is expressed in f/2, and the input data signal Din rises during the data 0 and falls during the data 1. A signal shown in FIG. 3(C) indicates that the name thereof is represented as the output q1 of the latch L1 (150), a fetch edge at the D terminal of the latch L1 (150) is indicative of the rising edge (as indicated as ↑CK) of the clock signal ckv, and the speed thereof is expressed in f/2. A signal shown in FIG. 3(D) indicates that the name thereof is represented as the output q2 of the latch L2 (151), a fetch edge at the D terminal of the latch L2 (151) is indicative of the falling edge (as indicated as ↓CK) of the clock signal ckv, and the speed thereof is expressed in f/2. A signal shown in FIG. 3(E) indicates that the name thereof is represented as the error signal (Error) of the exclusive-OR circuit 156, a logical expression indicative of the output of the exclusive-OR circuit 156 is expressed in q1 xor q2, and the speed thereof is f.
A signal shown in FIG. 3(F) indicates that the name thereof is represented as the output q3 of the latch L3 (152), a fetch edge at the D terminal of the latch L3 (152) is indicative of the falling edge (as indicated as ↓CK) of the clock signal ckv, and the speed thereof is expressed in f/4. A signal shown in FIG. 3(G) indicates that the name thereof is represented as the output q4 of the latch L4 (153), a fetch edge at the D terminal of the latch L4 (153) is indicative of the rising edge (as indicated as ↑CK) of the clock signal ckv, and the speed thereof is expressed in f/4. A signal shown in FIG. 3(H) indicates that the name thereof is represented as the reference signal (Ref) of the exclusive-OR circuit 157, a logical expression indicative of the output of the exclusive-OR circuit 157 is expressed in q3 xor q4, and the speed thereof is f/2.
As shown in FIGS. 3(A) through 3(C), the latch L1 (150) takes in or captures the input data signal Din (data 0) on the rising edge of the clock signal ckv and outputs it to the q1 output thereof. Since the clock signal ckv is High even if the input data signal transitions from the data 0 to the data 1, the q1 output holds the data 0. While the clock signal ckv is held Low, the data 1 of the input data signal Din appears at the output q1 as it is. When the input data signal Din transitions to the data 2, the data 2 appears at the output q1 as it is. Next, when the clock signal ckv rises while the input data signal Din is of the data 2, the latch L1 (150) takes in the data 2 and outputs it to the q1 output. Since the clock signal ckv is High even if the input data signal transitions from the data 2 to the data 3, the q1 output holds the data 2. Since such a process is similar subsequently, the description thereof will be omitted.
As shown in FIGS. 3(A), 3(B) and 3(D), the latch L2 (151) takes in the input data signal Din (data 1) on the falling edge of the clock signal ckv and outputs it to the q2 output thereof. Since the clock signal ckv is Low even if the input data signal transitions from the data 1 to the data 2, the q2 output holds the data 1. While the clock signal ckv is held High, the data 2 of the input data signal Din appears at the output q2 as it is. When the input data signal Din is caused to transition to the data 3, the data 3 appears at the output q2 as it is. Next, when the clock signal ckv falls while the input data signal Din is of the data 3, the latch L2 (151) takes in the data 3 and outputs it to the q2 output. Since the clock signal ckv is Low even if the input data signal transitions from the data 3 to the data 4, the q2 output holds the data 3. Since this is similar subsequently, the description thereof will be omitted.
When the output q1 is of the data 0 and the output q2 is of the data 1 as shown in FIGS. 3(C) through 3(E), the output of the error signal (Error) results in “(data 0) xor (data 1)” (hereinafter abbreviated as “0xor1”). Next, when the output q1 is of the data 1 and the output q2 is also of the data 1, the output of the error signal (Error) becomes “1xor1”=0. In FIG. 3(E), the output of the error signal (Error), which apparently reaches 0, is represented as the logical 0, and the output thereof which does not reach 0, is represented as a pulse like “0xor1”.
As shown in FIGS. 3(A), 3(B) and 3(E), when the input data signal Din is transitioned, the error signal (Error) is outputted as a pulse with the difference in time between a transient edge of the input data signal Din and the rising (or falling) edge of the clock signal ckv as a pulse width. Namely, when a position relationship (=±0.5×T) in which the rising (falling) edge of the clock signal ckv is placed in the center of the input data signal Din, is taken, the pulse width of the error signal (Error) results in ½ (=0.5×T) of the pulse width of the reference signal (Ref).
As shown in FIGS. 3(B), 3(C) and 3(F), the latch L3 (152) takes in the output q1 (data 0) on the falling edge of the clock signal ckv and outputs it to the q3 output thereof. Since the clock signal ckv is Low even if the output q1 transitions from the data 1 to the data 2, the q3 output holds the data 0. While the clock signal ckv is held High, the data 2 of the output q2 appears at the output q3 as it is. Next, when the clock signal ckv falls, the latch L3 (152) takes in the data 2 at the output q2 and outputs it to the q3 output. Since the clock signal ckv is Low even if the output q2 transitions from the data 3 to the data 4, the q3 output holds the data 2. Since this is similar subsequently, the description thereof will be omitted.
As shown in FIGS. 3(B), 3(D) and 3(G), the latch L4 (153) takes in the output q2 (data 1) on the rising edge of the clock signal ckv and outputs it to the q4 output thereof. Since the clock signal ckv is High even if the output q2 transitions from the data 2 to the data 3, the q4 output holds the data 1. While the clock signal ckv is held Low, the data 3 of the output q2 appears at the output q4 as it is. Next, when the clock signal ckv rises, the latch L4 (153) takes in the data 3 at the output q2 and outputs it to the q4 output. Since the clock signal ckv is High even if the output q2 transitions from the data 4 to the data 5, the q4 output holds the data 3. Since this is similar subsequently, the description thereof will be omitted.
When the output q3 is of the data 0 and the output q4 is of the data 1 as shown in FIGS. 3(F) through 3(H), the output of the reference signal (Ref) results in “0xor1”. Next, when the output q3 is of the data 2 and the output q4 is of the data 1, the output of the reference signal (Ref) becomes “2xor1” (or “1xor2”). In FIGS. 3(A) and 3(H), the reference signal (Ref) is always outputted as a pulse having a length width (=1.0×T) of the data cycle T where the input data signal Din has transitioned.
Thus, when the rising edge of the clock signal ckv is placed forward by Δt from the center of the input data signal Din, the error signal (Error) reduced by Δt in pulse width with respect to the pulse width (=0.5×T) equal to one-half the reference signal (Ref) is outputted. On the other hand, when the rising edge of the clock signal ckv is placed backward by Δt from the center of the input data signal Din, the error signal (Error) whose pulse width is increased by Δt with respect to the pulse width (=0.5×T) equal to one-half the reference signal (Ref), is outputted. Thus, the pulse width of the error signal (Error) results in 0.5×T±0.5×T.